Interrupts

• Interrupt Overview and IRQ Assignments
• TIG Bus Interupt Assignments (IRQ_0/IRQ_1)
• Real Time Clock Interrupt (IRQ_2)
• Halt Interrupt
• ISA Interrupts
• Fan Fault Interrupt
• TIG Interrupt Processing

Interrupt Overview and IRQ Assignments

These interrupts need to be posted via the TIG bus to the Tsunami C-Chip where they are collected in the Device Interrupt Register before being sent to the Alpha 21264 processor via the TIG bus. Programmable masking of interrupts is also done in the C-Chip using the Interrupt Mask Register.

All interrupts collected via the TIG Bus are level interrupts. In other words, these interrupt conditions remain present until cleared at the source through programmed I/O. The TIG Bus Interrupt posting buffers are not the real source of the interrupts and merely reading them will not clear the interrupt condition.

All ISA device interrupts are gathered by the Cypress Bridge chip and presented to the TIG Bus as a single level interrupt called INTR. All the rest of the System Board interrupts including PCI, errors and power status are allocated as shown in the following table.

TIG Bus Interrupt Assignments

Real Time Clock Interrupt

In addition to these interrupts, the System Board also sends the Square Wave from the Cypress Real Time Clock to the C-Chip. The C-Chip uses the Square Wave positive edges to record Interval Timer Interrupts through C-Chip MISC register. This interrupt is routed to CPU IRQ_2.

Halt Interrupt

When running Tru64 UNIX and OpenVMS, the front panel Reset button is configured by SRM to generate a Halt interrupt to the Alpha 21264 processor. This is done with a state internal to the PIC power management microcontroller.

This interrupt will be sent on Interrupt Bit [58] of the C-Chip Device Interrupt Register. The Alpha 21264 processor will receive this interrupt on IRQ_0 which is the same as the error interrupts.

Various catastrophic or operator-induced conditions cause a Halt to the SRM console.

ISA Interrupts

The following table indicates the ISA interrupt assignments. Note that the ISA interrupts are collected in the Cypress bridge using two 8259 compatible interrupt controllers in the same fashion as the Intel SIO bridge. Some of the ISA devices (Keyboard/Mouse, RTC) are embedded inside the Cypress chip while others are external. Each interrupt condition is maskable.

¹ IRQ5 is reserved for use with audio. IRQ7 is reserved for use by the parallel port. IRQ10 is reserved for use by the USB controller, regardless of whether it is enabled.

Note: AlphaBIOS sets up for audio use of IRQ5 at system power-on before it checks for any user-preference selections. Once IRQ5 is set up, it cannot be undone; therefore, IRQ5 can only be used for audio. Audio does not work with IRQ7, and it is important that users do not attempt to override the default.

Fan Fault Interrupt

The Fan_Fault interrupt is generated when the fan fault circuitry on the MLB detects a fan failure. This interrupt cannot be cleared until the error condition goes away. The normal response to this interrupt would be record the error and perform a graceful shutdown.

TIG Interrupt Processing

The C-Chip is responsible for collecting interrupts off the TIG bus. It does this continually in the background as a low-priority activity on the TIG Bus. An interrupt gathering cycle consists of reading all the interrupt bytes selected (the Compaq AlphaStation XP1000 System has 5), updating the Raw Device Interrupt Register and the Masked Device Interrupt Register in the C-Chip and finally performing a write to the Alpha 21264 processor IRQ register on the TIG DATA Bus. This entire interrupt gathering cycle is automatic.